One design and one enclosure for both models, whichever solution it runs. The summary is below; the block diagram, the terminal-block pin definition and the full electrical and mechanical figures are in the hardware specification.
FLS-HS-ER0 v3.2 · 11 pages · block diagram, pin definition, SWD debug header (section 3.3), electrical, mechanical, certification, ordering.
The Quick Start, the User Manual, the hardware specification and the example code download directly; for the System Integration Guide, leave your company details in a short form. All FLSEMI documents →
What the gateway does, a first installation, the status light, the live view, and integration at a glance — ports and the Modbus register blocks in outline.
BFi53ER0-BF firmware 0.57.82 · v1.8 · 9 pages
BFi53ER0 / BFi53ER0S: block diagram, terminal layout, SWD debug header, electrical, mechanical, certification and ordering.
FLS-HS-ER0 v3.2 · 11 pagesReceive every telegram over UDP, read the TCP feed with catch-up, and make a first Modbus TCP read — standard library only, free to use, copy and modify for BFi53ER0 integration.
3 programs + README · v1.1Firmware updates. Firmware images and their release notes are not published on this site. Write to hello@flsemi.us with the model, part number and firmware version on the System page, and we send what applies.
| Processor | Dual Arm Cortex-M33 — application core 128 MHz, network core 64 MHz |
|---|---|
| Memory | 1 MB flash, 512 KB RAM, 2 MB QSPI flash; network core 256 KB flash, 64 KB RAM |
| Security | Arm TrustZone, CryptoCell-312 |
| Radio | 2.4 GHz Bluetooth LE (Mesh, Long Range) and IEEE 802.15.4, through the on-board front-end module |
| Package | 12 × 16 mm, M.2 LGA board-to-board |
| Module approvals | NCC · CE · FCC · IC · TELEC · NBTC · Bluetooth |
The −40 to +105 °C figure is the core module’s own rating.
| Role | DECT NR+ radio running our own BFi91NR7DLCVG stack (ETSI TS 103 636) |
|---|---|
| Bands | 1.9 GHz (band 1) and 915 MHz (band 4), chosen at start-up |
| Transmit power | +21 dBm at 1.9 GHz, +19 dBm at 915 MHz |
The dashed block is fitted on the BFi53ER0S only; the field interfaces shown are those of the BFi53ER0. Pin definition, electrical and mechanical figures are in the hardware specification (PDF).
Front view with the Ethernet port below: odd terminals on the left with 01 at the top, even terminals on the right with 02 at the top. Terminal names match the case label. BFi53ER0S: terminal assignment to be announced.
